Design Techniques and Considerations for a 1.2V 10bit CMOS Pipeline ADC

Abstract

A 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33LSB respectively, while SNDR is 57.7dB.