Simulation methodology for enhancement of power delivery network decoupling

Abstract

The following paper presents the simulation methodology for optimizing the decoupling network of an integrated circuit like a processor or a Field Programmable Gate Array. The efficiency of simulation tools from commercial electronic computer aided design solution is demonstrated by correlating simulation results with measurement for S parameters analysis of bare PCB and the PCB associated with decoupling capacitors thanks to a dedicated test vehicle equipped with SMA connectors allowing S12 parameter measurement. An integrated module of the commercial solution calculating mounted inductance of capacitors is also presented as it is an essential element for decoupling optimization. Design flow is then given for optimizing the decoupling performance of a capacitor network in the case of reusing a electronic design. Surface occupied by decoupling components is firstly reduced and its efficiency increased by reducing mounted inductance. Performances of decoupling network are then analyzed in order to remove all unnecessary elements.