Design and Implementation of a Wide-bandwidth Digitally Controlled 16-phase Converter

Abstract

In this paper we present design and implementation of a 16-phase digitally controlled converter with 1.56 MHz per-phase switching frequency, 25 MHz sampling rate, and the closed-loop bandwidth of approximately 1 MHz. The experimental system includes 16 buck converters, a digital multi-phase modulator and a digital controller implemented on an FPGA. Direct digital design of the compensator is based on a multi-level converter model. A preorder arrangement of phases is used to minimize the output ripple. A zero-error-bin approach addresses the effects of phase-mismatches and sub-harmonic ripples on the stability of the wide-bandwidth controller. Simulation and experimental results show that very wide bandwidth operation and very fast transient responses are feasible even in the presence of significant phase mismatches