Comparison of NMOS and CMOS TFT inverters fabricated by LPCVD and SPC techniques at low temperature (<600/spl deg/C)

Abstract

After several experimental studies on improvement of the electrical performances of N-type polysilicon thin-film transistors (NMOS-TFT) fabricated by LPCVD (Low Pressure Chemical Vapor Deposition) and SPC (Solid Phase Crystallization) techniques at low temperature, it was necessary to implement a process to design a complementary TFT cell technology (CMOS-like TFT). This elementary cell is useful indeed essential to design efficient digital circuits. This paper describes the process developed and presents a comparison between two inverters: NMOS-inverter based on the use of two NMOS-TFTs and a CMOS-like TFT inverter. This work has allowed to validate the process and to quantify the improvement of the electrical characteristics such as noise margins, gain and output voltage amplitude.