High Integrated & Low Area DC-DC Buck Converter for the Wireless Applications in 65 nm CMOS

Chunzhong Guo, L. Sang
{"title":"High Integrated & Low Area DC-DC Buck Converter for the Wireless Applications in 65 nm CMOS","authors":"Chunzhong Guo, L. Sang","doi":"10.1109/CSRSWTC56224.2022.10098338","DOIUrl":null,"url":null,"abstract":"In this paper, a wireless module is presented using a high-efficiency and low-area current-mode DC-DC buck converter with an on-chip current sensor for feedback control. The DC-DC converter was fabricated using a standard 65 nm CMOS process and has a 1.1 mm2area. Its output voltage drops to 1.2 V from 2.5 V-3.6 V input, with an output ripple voltage of about 10 mV. To decrease the size of the external device while retaining high efficiency, a 2 MHz switching frequency and 2.2 μH inductance were chosen. Power efficiency exceeds 80% for output current ranging from 50 to 850 mA.","PeriodicalId":198168,"journal":{"name":"2022 Cross Strait Radio Science & Wireless Technology Conference (CSRSWTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 Cross Strait Radio Science & Wireless Technology Conference (CSRSWTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSRSWTC56224.2022.10098338","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

In this paper, a wireless module is presented using a high-efficiency and low-area current-mode DC-DC buck converter with an on-chip current sensor for feedback control. The DC-DC converter was fabricated using a standard 65 nm CMOS process and has a 1.1 mm2area. Its output voltage drops to 1.2 V from 2.5 V-3.6 V input, with an output ripple voltage of about 10 mV. To decrease the size of the external device while retaining high efficiency, a 2 MHz switching frequency and 2.2 μH inductance were chosen. Power efficiency exceeds 80% for output current ranging from 50 to 850 mA.
65纳米CMOS无线应用的高集成低面积DC-DC降压变换器
本文提出了一种采用高效率、低面积电流模式DC-DC降压变换器和片上电流传感器进行反馈控制的无线模块。该DC-DC变换器采用标准的65纳米CMOS工艺制造,面积为1.1 mm2。其输出电压从2.5 V-3.6 V的输入降至1.2 V,输出纹波电压约为10 mV。为了在保持高效率的同时减小外部器件的尺寸,选择了2 MHz的开关频率和2.2 μH的电感。功率效率超过80%,输出电流范围从50到850毫安。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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