{"title":"Toward a graphical tool for image and video processing embedded systems design","authors":"N. Zhar, M. A. Ali, M. Eleuldj","doi":"10.1109/INTECH.2012.6457762","DOIUrl":null,"url":null,"abstract":"In this paper we identify the requirements of a design tool for the implementation of image and video processing algorithms in hardware platforms such as FPGA or ASIC. We discuss the advantages and weaknesses of some existing design languages. Finally, we propose our solution, in compliance with specified requirements, which intends to bypass the shortcomings of existing languages by providing a high-level of abstraction through two kinds of diagrams; structural diagram and filter edition diagram. It also allows a formal verification and automatic code generation for an ASIC or a FPGA implementation.","PeriodicalId":369113,"journal":{"name":"Second International Conference on the Innovative Computing Technology (INTECH 2012)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Second International Conference on the Innovative Computing Technology (INTECH 2012)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INTECH.2012.6457762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper we identify the requirements of a design tool for the implementation of image and video processing algorithms in hardware platforms such as FPGA or ASIC. We discuss the advantages and weaknesses of some existing design languages. Finally, we propose our solution, in compliance with specified requirements, which intends to bypass the shortcomings of existing languages by providing a high-level of abstraction through two kinds of diagrams; structural diagram and filter edition diagram. It also allows a formal verification and automatic code generation for an ASIC or a FPGA implementation.