Effect of Process Variation on the Performance of Phase Frequency Detector

Abstract

In this paper, the effect of process variation in transistors on the phase noise in a conventional CMOS phase frequency detector (PFD) is investigated. When a phase locked loop (PLL) is locked the logical operations of the NAND gates in a PFD can be modeled on the basis of an inverter. Hence the authors consider a CMOS inverter in the TSMC18RF technology and analytically derive expressions for phase noise. Based on the analytical model, the effects of process parameter variations on the PFD are verified through Monte Carlo simulations. The resulting spread obtained for a cumulative variation of the parameters was 1dBc/Hz, indicating that the PFD is quite robust to process parameter variations. Finally, the gates contributing to the phase noise of the PFD are identified