A Nano-Structure Memory With SOI Edge Channel And A Nano Dot

Abstract

11. Device Fabrication The ultra-thin SO1 film was formed by thermal oxidation of SIMOX wafers. The thickness of the recessed top-silicon layer was about 41nm. The edge region was formed by reactive ion etching, Then, the gate oxide was thermally grown to a thickness of about 14nm. Poly-silicon sidewall was formed by LPCVD and RIE etchback (Fig. 2). The thickness of the remained poly-silicon at the sidewall was determined by RIE etchback time. The poly-silicon remained at the side wall was patterned by E-beam lithography to form a nano-dot (Fig. 3). The poly-silicon dot acts as the floating gate for the storage of electrons. Interpoly oxide was deposited to a thickness of about 50nm. And then poly-silicon was deposited, and control gate was pattemed optically. As shown in Figure I@), oxide on top of the channel was very thick, whereas the gate oxide on the edge was thin. So, the inversion layer is formed only at the side edge. Both devices with dot and without dot were fabricated.