Optimization of a digital neuron design

Abstract

Summary form only given, as follows. Artificial neural network models, composed of many nonlinear processing elements operating in parallel, have been extensively simulated in software. The real estate required for neurons and their interconnections has been the major hindrance for hardware implementation. Therefore, a reduction in neuron size is highly advantageous. A digital neuron design consisting of an arithmetic logic unit (ALU) has been implemented to conform to the hard-limiting threshold function. Studies on reducing the ALU size, utilizing Monte-Carlo simulations, indicate that the effect of such a reduction on network reliability and efficiency is not detrimental. Neurons with reduced ALU size operate with the same computational abilities as full-size neurons.<>