High-spatial-frequency MOS transistor gate length variations in SRAM circuits

Abstract

SRAM circuits have been used as electrical test structures to study short range spatial variations of MOS transistor effective gate length. Layout-dependent periodic errors were found to take up 30% to 90% of the total observed error variance, depending on the spatial frequency range and specific measurement grid used. Peaks in the measured gate-length error spatial spectrum were related to the periodicities existing in the circuit layout, and lithography simulations were done to identify the error sources. It was found that proximity effects, overlay errors due to stepper lens aberration, and pattern dependent coma effects contributed to a large percentage of the high spatial frequency errors observed.