Wire bonding process impact on low-k dielectric material in damascene copper integrated circuits

Abstract

This study investigates wire bonding impact on low-k dielectric material used in dual damascene copper integrated circuits. The paper focuses on wire bond process optimization required for devices with soft low-k dielectric material compared to device with hard standard silicon dioxide dielectric. A fine pitch (60 /spl mu/m bond pitch) wire bonding process was established on test vehicles with SiO/sub 2/ and low-k SiLK dielectrics. All wire bond process parameters were established on the SiO/sub 2/ test vehicle. The process optimization was carried out with emphasis on free air ball formation, first bond and wedge bond. Optimized process parameters were chosen from the process window and confirmation wire bond analysis was carried out on the SiO/sub 2/ test vehicle. The same bond parameters were implemented on the low-k SiLK test vehicle, and were found to induce deformation of the low-k dielectric layer, resulting in the peeling of bond pad from the low-k dielectric. The wire bonded samples were subjected to ball shear and wire pull test. In the SiO/sub 2/ dielectric test vehicle, failure was always in the ductile Au ball during ball shear and at the neck during pull test. In the low-k SiLK test vehicle, the initial failures were bond pads tearing off the low-k dielectric. This paper discusses the bonding process optimization carried out in order to solve this issue and to achieve good bonding. This paper also reports the reliability of these devices under temperature cycle, high thermal storage and PCT (pressure cooker test) tests. Detailed failure analysis carried out on the bond pad failure is also reported.