An FPGA implementation of low-latency video transmission system using lossless and near-lossless line-based compression

Abstract

In this paper, we present an FPGA implementation of low-latency video transmission system. The proposed system is capable of lossless video transmission using line-based compression. Assuming transmission over wireless communication channel where the data throughput dynamically changes, our system supports lossless to near-lossless scalable compression. According to the FPGA implementation result, we confirmed that our system can archive 45% of data reduction in average and can be implemented using 14,777 slice LUTs and 4,343 slice registers.