Low Power 3-Bit Flash ADC Design with Leakage Power Reduction at 45 nm Technology

Abstract

Most of the signals encountered in real world are analog in nature. Analog-to-digital converters are needed for conversion of an analog signal into digital signal. These converters can be implemented by using different available architectures. The performance of a converter is mainly analyzed based on its speed, area and power. Selection of a particular architecture totally depends upon its application. In this paper, the focus is on dynamic power, static power and delay of an ADC. Threshold Modified Comparator Circuit (TMCC) is used to reduce power dissipation. The work includes use of Self Controllable Voltage Level (SVL) technique to design a flash ADC for reduction of the leakage power. The simulation results of such ADC have been compared at 180 nm and at 45 nm technology. The proposed ADC has 41.12 μW dynamic power dissipation at 10 MHz frequency and 2.12 n W static power dissipation for 1.8 V at 45nm technology node. This data gets reduced to 1.866 μW dynamic power dissipation at the same frequency and static power gets reduced to 119.3 pW for 1.1V at 45nm. The software used for the designing and analysis purpose is Cadence Virtuoso version IC6.1.5.500.14.