Bit precision study of a non-orthogonal iterative detector with FPGA modelling verification

Abstract

Much work has been done on a non-orthogonal signal termed spectrally efficient frequency division multiplexing (SEFDM). Due to its self-created inter carrier interference (ICI), signal detection is complicated. A linear detector named iterative detection (ID) detector shows better bit error rate (BER) performance and complexity trade-off than other linear detectors. Therefore, this work shows the first time hardware modelling of the ID detector at the register transfer level (RTL) stage. The impact of bit precision on the system performance is studied at the beginning. Then, an RTL model is designed with results showing competitive fixed-point performance which are comparable to Matlab floating-point results. Verification work is operated in a co-simulation environment through comparison between fixed-point Matlab results and ISim (a hardware modelling software from Xilinx Inc.) simulation results. Their results are consistent indicating the hardware model is correct.