Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM

Abstract

This work proposes a body-biasing technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. Accounting for the process variation, the operating voltage, Vmin, is estimated at 6-sigma yield. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. In high-performance mode, the optimized Vmin is reduced to 0.491 V at back bias of 0.2 V. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.