A programmable simulator for analyzing the block data flow architecture

Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems Pub Date : 1994-01-31 DOI:10.1109/MASCOT.1994.284391

S. Alexandre, W. Alexander, D. Reeves

引用次数: 5

Abstract

A programmable simulator has been developed for analyzing the performance of a class of parallel computers. The simulator provides detailed information about the timing, resource usage, and output results for an algorithm executing on the parallel computer. A user specifies the configuration and performance characteristics of the computer to be simulated. The user also describes the algorithm to be executed on the computer. The use of the simulator for QR factorization is briefly described and the results are presented. Our approach is compared with other simulation methods.<>

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用于分析块数据流体系结构的可编程模拟器

为分析一类并行计算机的性能，设计了一个可编程模拟器。模拟器为并行计算机上执行的算法提供有关时序、资源使用和输出结果的详细信息。用户指定要模拟的计算机的配置和性能特征。用户还描述了要在计算机上执行的算法。简要介绍了该模拟器在QR分解中的应用，并给出了仿真结果。并与其它仿真方法进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems

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