On scheduling using parallel input-output queued crossbar switches with no speedup

S. Mneimneh, V. Sharma, Kai-Yeung Siu
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引用次数: 9

Abstract

We propose an efficient parallel switching architecture (PSA) that requires no speedup and guarantees bounded delay. Our architecture consists of /spl kappa/ crossbar switches operating in parallel under the control of a single scheduler, with /spl kappa/ being independent of N the number of inputs and outputs of the PSA. Arriving traffic is demultiplexed (spread) over the /spl kappa/ identical crossbar switches, switched to the correct output, and multiplexed (combined) before departing from the parallel switch. We show that by using an appropriate demultiplexing strategy at the inputs and by applying the same matching at each of the /spl kappa/ parallel crossbar switches during each slot, our scheme guarantees that the cells of a flow can be read in FIFO order from the output queues of the crossbar switches, thus eliminating the need for cell resequencing. Further, by allowing the PSA scheduler to examine the state of only the first of the /spl kappa/ parallel switches, our scheme also reduces considerably the amount of state information required at the scheduler. The scheduling algorithms that we develop are based on existing practical scheduling algorithms for crossbar switches, and have an additional communication complexity that is optimal up to a constant factor. Our approach also provides a way to build a high capacity switch/router that can support line rates that are higher than the speed at which the parallel switches themselves operate.
无加速的并行输入输出排队交叉开关调度研究
我们提出了一种不需要加速且保证有界延迟的高效并行交换架构。我们的架构由/spl kappa/交叉开关组成,在单个调度程序的控制下并行操作,/spl kappa/与PSA的输入和输出数量N无关。到达的流量在/spl kappa/相同的交叉开关上被解复用(传播),切换到正确的输出,并在离开并行交换机之前被复用(合并)。我们表明,通过在输入端使用适当的解复用策略,并通过在每个插槽中对每个/spl kappa/并行交叉条开关应用相同的匹配,我们的方案保证了流的单元可以以FIFO顺序从交叉条开关的输出队列中读取,从而消除了对单元重排序的需要。此外,通过允许PSA调度器仅检查/spl kappa/并行开关中的第一个开关的状态,我们的方案还大大减少了调度器所需的状态信息量。我们开发的调度算法是基于现有的跨排交换机的实际调度算法,并且具有额外的通信复杂性,可优化到一个常数因子。我们的方法还提供了一种构建高容量交换机/路由器的方法,该交换机/路由器可以支持比并行交换机本身运行速度更高的线路速率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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