Multi Gigabit Transceiver Configuration RAM Fault Injection Response

Abstract

High performance processing and memory systems require enormous amounts of I/O bandwidth. Wide parallel bus architectures have reached their practical limits for high bandwidth transport. High speed serial interfaces that support 10's of Gbps are now displacing wide shared bus architectures for many systems. Xilinx FPGAs serial links support this transition by providing more than 10 Gbps in their multi gigabit transceiver (MGT) I/Os. For space applications, these links are susceptible to single event effects (SEE). Many of these effects are due to upsets in the FPGAs configuration RAM that control the many features and functions of the I/O. This paper details the functional effects of configuration RAM upsets in Xilinx MGTs. These effects are realized by injecting upsets in the FPGA configuration RAM while monitoring MGT functional operation. Configuration RAM upset effects are described and functional upset rates due to configuration RAM upsets are calculated for an example orbit. The results of this work provide insight into the on-orbit upset rate and effects of Xilinx multigigabit transceivers