A physical resist shrinkage model for full-chip lithography simulations

Abstract

Strong resist shrinkage effects have been widely observed in resist profiles after negative tone development (NTD) and therefore must be taken into account in computational lithography applications. However, existing lithography simulation tools, especially those designed for full-chip applications, lack resist shrinkage modeling capabilities because they are not needed until only recently when NTD processes begin to replace the conventional positive tone development (PTD) processes where resist shrinkage effects are negligible. In this work we describe the development of a physical resist shrinkage (PRS) model for full-chip lithography simulations and present its accuracy evaluation against experimental data.