On the design of a selftesting WSI multiplier array

[1989] Proceedings International Conference on Wafer Scale Integration Pub Date : 1989-01-03 DOI:10.1109/WAFER.1989.47561

U. Ramacher, J. Beichter, W. Kamp

引用次数: 2

Abstract

The design of a 6.8*6-cm wafer-scale integration (WSI) chip for matrix-matrix multiplication, the layout, and its verification hierarchy are described. The chip is designed in a defect-tolerant style. Whole wafer lithography resulting in 2- mu m effective design rules was chosen because of reduced costs of masks.<>

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一种自测WSI乘法器阵列的设计

介绍了一种用于矩阵乘法的6.8*6 cm晶圆级集成(WSI)芯片的设计、布局和验证层次。该芯片采用容错风格设计。由于掩模成本较低，选择了2 μ m有效的全晶圆光刻设计规则

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

[1989] Proceedings International Conference on Wafer Scale Integration

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