Design and implement for test in a complex system on chip

Abstract

With the increasing complexity and chip scale of SoC, DFT (Design-for-test) has become a more important and difficult process. A system-level DFT strategy for a SoC based on 32-bit RISC CPU is presented. According to the characteristic of different parts of SoC, test solutions for digital logic, SRAM and CPU Core in the SoC are discussed. The test methods include internal scan design, MBIST, BSD and function test. The results show the higher fault coverage and smaller area overhead are gotten.