{"title":"High-voltage driving circuit with on-chip ESD protection in CMOS technology","authors":"Chun-Yu Lin, Yan-Lian Chiu","doi":"10.1109/ICIIBMS.2017.8279758","DOIUrl":null,"url":null,"abstract":"A high-voltage / high-power driving circuit for the applicatrions such as a motor controller in robot is presented in this work. The driving circuit is further equipped with a novel electrostatic discharge (ESD) protection design to enhance its reliability. A 3×VDD-tolerant driving circuit with on-chip ESD protection is demonstrated using a 0.18 μm CMOS process with Vdd of 3.3V. The ESD robustness can be improved without the use of any additional ESD protection device or layout area. Furthermore, this design technique can be used for an n∗Vdd-tolerant driving circuit with improved ESD robustness.","PeriodicalId":122969,"journal":{"name":"2017 International Conference on Intelligent Informatics and Biomedical Sciences (ICIIBMS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Intelligent Informatics and Biomedical Sciences (ICIIBMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIIBMS.2017.8279758","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A high-voltage / high-power driving circuit for the applicatrions such as a motor controller in robot is presented in this work. The driving circuit is further equipped with a novel electrostatic discharge (ESD) protection design to enhance its reliability. A 3×VDD-tolerant driving circuit with on-chip ESD protection is demonstrated using a 0.18 μm CMOS process with Vdd of 3.3V. The ESD robustness can be improved without the use of any additional ESD protection device or layout area. Furthermore, this design technique can be used for an n∗Vdd-tolerant driving circuit with improved ESD robustness.