Clock routing for high-performance ICs

Abstract

Routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of-gate, etc.) application-specific ICs (ASICs) are addressed. In previously reported works, the routing of a clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock-routing problems. The authors present a novel approach to the clock-routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions a decrease in skew with an increase in net size was proven theoretically and observed experimentally. A two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree was observed.<>