The dynamic relocation cache and its energy consumption model for low power processor

Abstract

In this paper, a dynamic relocation cache scheme is proposed for low power processor. Based on an energy consumption function of cache system, which mapping the cache energy consumption problem to a binary ILP (Integer Linear Programming) problem, this dynamic relocation cache scheme map the static code to a dynamic location through an address mapping strategy which can relocate the compiler generated code to a single memory with execution sequence, thus provide high performance with small memory capacity. Finally, the full RTL model based on LEON2 processor is implemented and simulated, and the experiment results show that the energy consumption of this cache scheme have approximate 25% improvement comparing to traditional direct cache scheme for achieving the same IPC (Instructions Per Clock).