Effect of surface-trap levels on threshold-voltage change in GaAs FETs

Abstract

Compound semiconductor FETs have begun to be used for applications which need high-speed and high-voltage operation. It becomes very important to reduce threshold-voltage change with respect to drain voltage in such applications requiring large amplitude outputs. For high-voltage operation, important results on gate breakdown and on I-V kinks have been obtained using two-dimensional device simulations. However, threshold-voltage change has not been investigated fully. In this study, we analyze the effect of surface trap levels on threshold-voltage change. We used 0.3-micron gate doped-channel heterostructure insulated-gate FETs in this study.