Development of a Dual GCT

Abstract

The performance of high-power inverters strongly depends on the characteristics of the underlying semiconductor device. The design of such devices is typically a compromise between on-state losses and switching losses. The idea analyzed in this paper is to combine two GCT devices into one single wafer, one switching-optimized GCT structure and one conducting-optimized GCT. By a parallel connection of both devices and a good trigger sequence of the gate signals, a higher performance can be achieved in comparison to a single GCT. More advantages of the Dual GCT are qualified in [1]. In this paper, the Dual GCT concept is discussed in relation to standard GCTs and two single GCTs in parallel mode. Additional FEM simulations of these GCTs demonstrate the advantages of the Dual GCT quantitatively.