An efficient hardware design for intra-prediction in H.264/AVC decoder

Abstract

The H.264/AVC intra-frame codec is widely used to compress image/video data for applications like Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video. Intra-prediction is one of the top 3 compute-intensive processing functions in the H.264/AVC baseline decoder [6] and, therefore, consumes significant number of compute cycles a processor. In this paper, we propose a configurable, high-throughput, and area-efficient hardware design for the intra-prediction unit. The intra-prediction algorithm is optimized to significantly reduce the redundancy in addition operations (e.g., 27% reduction when compared with state-of-the-art in literature [12]). The area requirement for our hardware implementation of the optimized intra-prediction algorithm is further reduced by employing a configurable design to reuse data paths for mutually exclusive processing scenarios. The proposed design is described in VHDL and synthesized under 0.18μm CMOS standard cell technology. While working at a clock frequency of 150 MHz, it can easily meet the throughput requirement of HDTV resolutions and consumes only 21K gates.