Functional unit level parallelism in RISC architecture

Abstract

This paper presents the design and implementation of RISC processor having five stages pipelined architecture. Functional unit parallelism is exploited through the implementation of pipelining in five stages of RISC processor. The hazards which come to life due to parallelism are data, structural, and control hazards. In order to achieve the true benefits of the parallelism through pipelining; these hazards must be properly handled. The data hazards are solved using bypassing in which we forward the required value of the operand to the succeeding instruction. Structural hazards are solved by implementing three port register file so that two operand reading and one register writing can be performed in parallel without degrading the performance. Control hazards arise from Branch, Jump and Call instructions. To solve these problems, we insert automated NOP in stage2, stage3 and stage4. The processor designed is a fully functional processor which can execute any program including jump statements, switch statements, loops and subroutines which are the basic ingredients of any computer program.