Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs on a Multi-Core Processor

Abstract

The AUTOSAR standard does not provide an approach for the mapping of its ECU software architecture to a message-based multicore system. In this work we present an analysis of performance and fault containment of a novel TIme-triggered MEssage-based multi-core architecture for AUTOSAR (TIMEA). The TIMEA platform is intended to bring the advantages of network-on-a-chip architectures to the AUTOSAR software, which lead to multiple benefits for fail operational real time systems such as temporal predictability and fault isolation. We introduce a fault hypothesis consisting of multiple fault assumptions and the definition of the fault containment regions and we describe the algorithms for the integration of a multicore monitoring service into the AUTOSAR Basic Software. A set of experiments were carried out to evaluate the performance of the system using an anti-lock braking use case in a simulation scenario under failure occurrences. The obtained results demonstrate how the TIMEA platform remains operational in the presence of failures.