Performance and implementation aspects of higher order head-of-line blocking switch boxes

Abstract

Nonuniform traffic can degrade the overall performance of multistage interconnection networks substantially. This performance degradation was traced back to higher order head-of-line blocking (higher order HOL-blocking) effects within the network in the literature. This paper further elaborates on higher order HOL-blocking networks, on their performance under nonuniform traffic patterns, and on methods on how to efficiently implement switch boxes to construct higher order HOL-blocking networks. An analytical upper bound of the achievable network bandwidth under nonuniform traffic patterns is derived and compared to simulation results. Furthermore, it is discussed how central memory buffered switch boxes can be efficiently changed into higher order HOL-blocking switch boxes through only minor changes in the switch box control path. With those switch boxes, high network performance under nonuniform traffic patterns can be achieved with regular hardware effort.