A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits

Abstract

A novel phase-locked-loop (PLL) topology for pulse width modulation (PWM) technique in high speed I/O circuits is presented in this paper. The VCO of the PLL generates the eight phase clocks of the same frequency. A simple level shifter structure is used to amplify the VCO output signal to the full voltage swing and guarantee 50% duty cycle for a wide range of frequency. The performance of the charge-pump and phase- frequency detector is improved from the previous research. The proposed PLL can be used in both transmitter end and receiver end and the performance satisfies the requirements of high speed wireline communication.