Random Error Detection and Correction Codes for Multiple Bits

Abstract

The utilization of error-correction codes (ECCs) in conjunction with the most recent correction capabilities may be a general design level strategy for making memories more resistant to Multiple Bit Upsets (MBUs). This general strategy led to the problem in developing the algorithm that gives us advanced error correction and low redundancy, mainly with adjacent ECCs. Up to 3 bit burst error correction is only possible with the existing technologies that go hand in hand with the MBU's mainly due to the scaling factors and the decrement in the distance of cell interval. With this, it is clear that the previous technologies are not meeting the application reliability requirements especially in unfavorable conditions. In order to provide a novel approach even in unfavorable conditions, an algorithm is proposed with existing Burst Error Correction (BEC) codes with Multibit Error Correction (MBEC). Initially the planning methods are defined following a search algorithm to search out the codes which accommodates the proposed methods. The H matrix which is obtained and evaluated relative to the 3 bit BEC along with MBEC is presented. Check bit comparison for no additional redundancy is done with respect to 3 bit BEC. Enhancement in the performance is observed with the application of new algorithm in 3 bit BEC when compared to previous codes. Xilinx ISE library is used to implement encoders and the decoders. This implementation provides us with additional information in terms of total area improvement and a delay mechanism for realizing correction abilities.