Bappaditya Mondal, Chandan Bandyopadhyay, H. Rahaman
{"title":"Online testing of SMGF in ESOP based reversible circuit","authors":"Bappaditya Mondal, Chandan Bandyopadhyay, H. Rahaman","doi":"10.1109/TECHSYM.2016.7872671","DOIUrl":null,"url":null,"abstract":"This work presents an online testing scheme for detecting Single Missing Gate Faults (SMGF) in Exclusive-Or Sum of Product (ESOP) based reversible circuits consisting of both the positive and negative control MCT (Multiple control Toffoli) gates. In this technique, initially we transform an input function to its equivalent testable design, where some redundant gates and an ancillary line are appended to the design. After that, the test vectors are applied to the input of the circuit for detecting all possible faults in the design. This scheme has been tested successfully over large benchmark circuits to verify correctness of the algorithm. Performance of the proposed design has been compared with the existing well known testing algorithms, and improvement over them has been observed.","PeriodicalId":403350,"journal":{"name":"2016 IEEE Students’ Technology Symposium (TechSym)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Students’ Technology Symposium (TechSym)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TECHSYM.2016.7872671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work presents an online testing scheme for detecting Single Missing Gate Faults (SMGF) in Exclusive-Or Sum of Product (ESOP) based reversible circuits consisting of both the positive and negative control MCT (Multiple control Toffoli) gates. In this technique, initially we transform an input function to its equivalent testable design, where some redundant gates and an ancillary line are appended to the design. After that, the test vectors are applied to the input of the circuit for detecting all possible faults in the design. This scheme has been tested successfully over large benchmark circuits to verify correctness of the algorithm. Performance of the proposed design has been compared with the existing well known testing algorithms, and improvement over them has been observed.