Decoupling Capacitor Optimization for Flat $\mathrm{Z}$ PCB Power Distribution Networks

H. Barnes, S. Sandler
{"title":"Decoupling Capacitor Optimization for Flat $\\mathrm{Z}$ PCB Power Distribution Networks","authors":"H. Barnes, S. Sandler","doi":"10.1109/EMCSI.2018.8495286","DOIUrl":null,"url":null,"abstract":"Power integrity applications suffer from the inability to precisely define the dynamic transient current. This has led to an increased interest in designing for a target impedance over a wide spectral bandwidth. Prior art has shown that a flat impedance design results in the lowest m V ripple excursion per Amp of step load. [1] This paper provides a simple method for estimating the required decoupling C for flat impedance. This method is then used to demonstrate the adverse effect of inductance in the PDN that requires an increase in the required total decoupling capacitance.","PeriodicalId":120342,"journal":{"name":"2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (EMC, SI & PI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMCSI.2018.8495286","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

Power integrity applications suffer from the inability to precisely define the dynamic transient current. This has led to an increased interest in designing for a target impedance over a wide spectral bandwidth. Prior art has shown that a flat impedance design results in the lowest m V ripple excursion per Amp of step load. [1] This paper provides a simple method for estimating the required decoupling C for flat impedance. This method is then used to demonstrate the adverse effect of inductance in the PDN that requires an increase in the required total decoupling capacitance.
平$\ mathm {Z}$ PCB配电网的去耦电容优化
功率完整性应用无法精确定义动态瞬态电流。这导致了在宽频谱带宽上设计目标阻抗的兴趣增加。现有技术表明,平坦阻抗设计导致每安培阶跃负载的最小毫伏纹波偏移。[1]本文提供了一种估算平坦阻抗所需去耦C的简单方法。然后使用该方法来演示PDN中电感的不利影响,该电感需要增加所需的总去耦电容。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信