A priority-based parallel architecture for sensor fusion

Abstract

The architecture described in this paper supports a wide (32-bit) priority field across the entire system, including processor elements and the interconnection network. The processing element has a hardware task queue to help manage tasks for two execution pipelines (one for executing tasks, and the other for communication). Its fast interrupt handling facility directly supports the wide priority field. The processing elements are connected via a prioritized multistage network that also supports the same wide priority field. Connecting up to 64 processors, the system offers the high performance in real-time processing needed for sensor fusion processing.<>