Wireless on Networks-on-Chip

Abstract

On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package. The wireless interconnects are typically considered as a hierarchical layer or a supplementary network utilized in a hybrid implementation with the traditional wire-based interconnects of the common network-on-chip implementations.