Initial results for automatic calibration of the LabPET II front-end detector module

Nadia Jurgensen, L. Arpin, H. Bouziri, L. Njejimana, K. Koua, Émilie Gaudin, J. Pratte, R. Lecomte, R. Fontaine
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引用次数: 1

Abstract

An automatic calibration process for the LabPET II detector front-end module has been developed. By aiming at sub-millimetric spatial resolution, an unprecedented channel density is reached. The new detector front-end module is based on an application-specific integrated circuit (ASIC) implementing a Time-over-Threshold (ToT) scheme to extract both energy and time information. Consequently manual channel calibration becomes a tedious task and an automatic calibration strategy adapted to the ToT scheme is required to cope with the huge number and complexity of detector channels. The calibration process involves four main tasks: Clock Phase Adjustment, Photopeak Alignment, Timing Optimization and Energy Correction. To grant an easy and frequent adjustment, the calibration routine must be automatic and real-time. It was implemented in VHDL and C on a Microblaze microprocessor core embedded in a field programmable gate array (FPGA). Misalignment between channels were reduced after calibration from 17% FWHM to 6% FWHM.
LabPET II前端检测器模块自动校准的初步结果
开发了LabPET II检测器前端模块的自动校准流程。以亚毫米级空间分辨率为目标,达到了前所未有的通道密度。新的检测器前端模块基于专用集成电路(ASIC),实现了时间超过阈值(ToT)方案,以提取能量和时间信息。因此,手动通道校准成为一项繁琐的任务,需要适应ToT方案的自动校准策略来应对检测器通道的数量和复杂性。校准过程包括四个主要任务:时钟相位调整、光峰对准、时序优化和能量校正。为了方便和频繁的调整,校准程序必须是自动和实时的。它是在Microblaze微处理器内核上用VHDL和C语言实现的,内核嵌入在现场可编程门阵列(FPGA)上。校正后通道间的不对准从17%的频宽降低到6%的频宽。
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