Universal ISA simulator with soft processor FPGA implementation

Abstract

We present a system that allows simulating wide range of instruction set architectures (ISA). This system includes full development and simulation environment for defining the required ISA, creating and editing assembly programs of the defined ISA, and simulating the execution of these programs. This system also includes a soft processor described in the Verilog hardware description language (HDL). This soft processor is synthesized from a customizable general processor template to implement the defined ISA on a field-programmable gate array (FPGA). This system provides an innovative, generic simulator for many architectures and for experimenting with new ones. It has a unique and easy-to-use interface that focuses on functionality rather than hardware implementation. This system was validated by successfully implementing several ISAs of various ISA classes such as MIPS, x86, and PIC. This system provides a flexible tool for teaching assembly language and computer architecture. Additionally, it provides an easily customizable soft processor that allows testing programs with real I/O interfacing circuits.