Design and analysis of fourth-order leapfrog topologies for sigma-delta A/D converters

Abstract

A novel design and analysis method for a 4th-order sigma-delta modulator (SDM or DSM) based on leapfrog topologies is presented. First, we discuss the arrangement of delayed and non-delayed type integrators for the leapfrog topologies and then determine a stable topology for analysis. Using the theoretical analysis including DC analysis and the relationship of roots and coefficients of an equation, the ranges of the loop coefficients which stabilize the system are determined. The numerical analysis is then adopted to analyze the ranges of the loop coefficients. According to the above analysis methods, the stable regions in frequency domain are easily determined. From these stable regions, a set of coefficients for VLSI implementation is chosen. The chosen loop coefficients of the leapfrog topologies are very simple and such that circuit complexity is reduced, To component variations, the performance of leapfrog SDM is less sensitive than that of leapfrog filter. Hence, circuit design becomes simpler and more effective. Behavior simulation shows that a 4th-order leapfrog topology can achieve the inband signal-to-noise ratio (SNR) more than 110 dB and the dynamic range (DR) more than 110 dB for 640 oversampling ratio. Besides, it also shows that both the gain ripple for inband signal and group delay variation are negligible, Hence, the leapfrog topologies can be used in ultra-high resolution signal processing system such as speech application, codec in digital cellular phone, and high precision measurement equipment.