{"title":"Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs","authors":"C. Kshirsagar, Mohamed N. El-Zeftawi, K. Banerjee","doi":"10.1145/1391469.1391533","DOIUrl":null,"url":null,"abstract":"Intrinsic and parasitic capacitances play an important role in determining the high-frequency RF performance of devices. Recently, a new type of carbon nanotube field effect transistor (CNFET) based on tunneling principle has been proposed, which shows impressive device properties and overcomes some of the limitations of previously proposed CNFET devices. Although carbon nanotube based devices have been optimized for DC performance so far, little has been done to optimize them for high-frequency operation. In this paper, we present, detailed modeling and analysis of device geometry based intrinsic and parasitic capacitances of tunneling carbon nanotube field effect transistors (T-CNFETs) with both single nanotube as well as nanotube-array based channel. Based on the model, we analyze scaling of parasitic capacitances with device geometry for two different scaling scenarios of T-CNFETs. We show that in order to reduce the impact of parasitic capacitance, nanotube density has to be optimized. Furthermore, for the first time, we analyze various factors affecting the high-frequency/RF performance of back gated T-CNFETs and study the impact of parasitic and screening effects on the high-frequency/RF performance of these devices.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 45th ACM/IEEE Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1391469.1391533","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
Intrinsic and parasitic capacitances play an important role in determining the high-frequency RF performance of devices. Recently, a new type of carbon nanotube field effect transistor (CNFET) based on tunneling principle has been proposed, which shows impressive device properties and overcomes some of the limitations of previously proposed CNFET devices. Although carbon nanotube based devices have been optimized for DC performance so far, little has been done to optimize them for high-frequency operation. In this paper, we present, detailed modeling and analysis of device geometry based intrinsic and parasitic capacitances of tunneling carbon nanotube field effect transistors (T-CNFETs) with both single nanotube as well as nanotube-array based channel. Based on the model, we analyze scaling of parasitic capacitances with device geometry for two different scaling scenarios of T-CNFETs. We show that in order to reduce the impact of parasitic capacitance, nanotube density has to be optimized. Furthermore, for the first time, we analyze various factors affecting the high-frequency/RF performance of back gated T-CNFETs and study the impact of parasitic and screening effects on the high-frequency/RF performance of these devices.