On the influence of arithmetic underflow rounding standard on the speed of FDTD modeling

2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535) Pub Date : 2004-06-06 DOI:10.1109/MWSYM.2004.1338949

M. Sypniewski, W. Gwarek

引用次数: 1

Abstract

This paper presents the influence of arithmetic underflow rounding operations on the speed of FDTD analysis. It is shown that the underflow treatment according to the IEEE standard 754 (commonly accepted and implemented in modern arithmetic processors) may sometimes result in drastic slowdown of the speed of computing. The effect is much more pronounced in some of the most modern and most used processors. The ways to circumvent the effect by specific software operations are discussed.

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算法下流舍入标准对FDTD建模速度的影响

本文讨论了算术下流舍入运算对时域有限差分分析速度的影响。结果表明，根据IEEE标准754(在现代算术处理器中普遍接受和实现)进行的下流处理有时会导致计算速度的急剧下降。在一些最现代和最常用的处理器中，这种效果更为明显。讨论了通过具体的软件操作来规避这种影响的方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)

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