Renyuan Zhang, Tati Erlina, T. Nguyen, Y. Nakashima
{"title":"Hybrid Stochastic Computing Circuits in Continuous Statistics Domain","authors":"Renyuan Zhang, Tati Erlina, T. Nguyen, Y. Nakashima","doi":"10.1109/socc49529.2020.9524786","DOIUrl":null,"url":null,"abstract":"A hybrid scheme of stochastic computing (SC) is explored by representing and processing the stochastic numbers (SNs) in multiple domains of continuous statistics space. On the basis of Neuron-MOS mechanism, pulses with arbitrary duty-cycles and various frequencies are efficiently generated. By interfering the pulses with multiple keys such as the level and frequency, the SNs are observed in continuous domain instead of long discrete bit-streams conventionally. Employing this stochastic representation, all of three typical SC fashions including straight multiplication/summation, Bernstein polynomial expansion, and finite state machine (FSM) are retrieved by the proposed hybrid schemes. For the Multiply-ACcumulations (MACs), the combination of pulse strength and duty-cycle performs the multiplication; the entanglement among various combinations above behaves accumulations; and the integral within a specific time window indicates the scale-free MAC result efficiently. For retrieving arbitrary functions in SC, the frequency interfering mechanism and novel multi-valued logic (MVL) multiplexer are employed to implement Bernstein polynomials with an ultra-compact VLSI circuit. Moreover, the continuous Markov chain is simply implemented by the SNs switching and a membrane capacitor for performing a special continuous state machine (CSM) which offers the SC sigmoid function with post-silicon scalability. From the circuit simulation results, the transistor amounts of proposed hybrid SC circuits are reduced to 6.1 %, 2.7%, and 8.3% of the state-of-art works for MAC, Bernstein polynomial, and FSM, respectively. Meanwhile, the performances over the accuracy, speed, and power consumption are all similar or superior to state-of-arts.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/socc49529.2020.9524786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A hybrid scheme of stochastic computing (SC) is explored by representing and processing the stochastic numbers (SNs) in multiple domains of continuous statistics space. On the basis of Neuron-MOS mechanism, pulses with arbitrary duty-cycles and various frequencies are efficiently generated. By interfering the pulses with multiple keys such as the level and frequency, the SNs are observed in continuous domain instead of long discrete bit-streams conventionally. Employing this stochastic representation, all of three typical SC fashions including straight multiplication/summation, Bernstein polynomial expansion, and finite state machine (FSM) are retrieved by the proposed hybrid schemes. For the Multiply-ACcumulations (MACs), the combination of pulse strength and duty-cycle performs the multiplication; the entanglement among various combinations above behaves accumulations; and the integral within a specific time window indicates the scale-free MAC result efficiently. For retrieving arbitrary functions in SC, the frequency interfering mechanism and novel multi-valued logic (MVL) multiplexer are employed to implement Bernstein polynomials with an ultra-compact VLSI circuit. Moreover, the continuous Markov chain is simply implemented by the SNs switching and a membrane capacitor for performing a special continuous state machine (CSM) which offers the SC sigmoid function with post-silicon scalability. From the circuit simulation results, the transistor amounts of proposed hybrid SC circuits are reduced to 6.1 %, 2.7%, and 8.3% of the state-of-art works for MAC, Bernstein polynomial, and FSM, respectively. Meanwhile, the performances over the accuracy, speed, and power consumption are all similar or superior to state-of-arts.