A FPGA based square-root coprocessor

Abstract

We present an FPGA implementation of a non-restoring integer square-root algorithm, that uses estimates for result-digit selection and radix-2 redundant addition in recurrence. On-the-fly conversion of the result-digit and signed-digit adder/substractor are used to simplify the hardware realization. Modifications of the equations for th optimal use of Xilinx CLBs, and the necessary CLB resources for different bit-length calculations are outlined, for the XC3000 family.