Analysis of carrier offset technique used in a five-level inverter scheme with emphasis on DC-link capacitor voltage balancing

Abstract

Amongst multi-level inverter topologies, neutral point clamped (NPC) inverter is widely used for inherent advantages offered by it compared to other topologies. The main drawback of NPC inverter is the fluctuation in the neutral point voltage and the corresponding imbalance created in dc-link capacitor voltages. A balancing scheme is proposed in this paper for five-level NPC inverter by providing offset in the individual carrier without using any extra hardware. In this scheme, only capacitor voltages are measured and not the load current. However, the limitation of this control scheme is that the wave shape of fundamental output voltage of the inverter is not as per the requirement. The output voltage has full dc-link voltage but waveform has only three levels when machine is operated in five-level mode. The quarter wave as well as half wave symmetry in an inverter output voltage is lost so harmonics in the output voltage waveform increases compared to sinusoidal pulse width modulation (SPWM) technique for the same level. The rms output voltage is more than that of an ideal NPC inverter. This will affect V/f ratio as well as torque of the motor. Also, dv/dt stress on switches increases due to less number of levels compared to ideal five-level NPC inverter. Simulation is carried out in MATLAB/Simulink. Hardware implementation of one leg of five-level neutral point clamped inverter with stiff dc power supply for each capacitor is carried out using dSPACE DS1104 controller board. The proposed scheme can be applied (for two-level and three-level modes) in conjunction with other hardware scheme used for balancing during four-level and five-level operation, leading to a hybrid balancing scheme.