A Drain Resistance Degradation Modeling Procedure of LDMOS's

Abstract

A complete aging circuit simulation method using a drain resistance degradation model of laterally-diffused MOSFETs (LDMOS's) is presented. The drain resistance degradation caused by the hot electron injection (HCI) effect in the drain drift region has been formulated, and then implemented in SPICE. A practical circuit aging simulation procedure has been demonstrated with LDMOS measurements for a fundamental DC-DC converter circuit, effectively.