Hanie Ghaedrahmati, Jianfeng Xue, J. Jin, Jianjun J. Zhou
{"title":"A 1mW 20MHz Bandwidth 9.51-ENOB Dynamic-Amplifier-Based Noise-Shaping SAR ADC","authors":"Hanie Ghaedrahmati, Jianfeng Xue, J. Jin, Jianjun J. Zhou","doi":"10.1109/CIRSYSSIM.2018.8525985","DOIUrl":null,"url":null,"abstract":"A 10-bit 160MS/s 20MHz bandwidth low-power noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) using a novel dynamic amplifier-based filter is presented. Thanks to noise-shaping architecture, the proposed scheme can achieve 10-bit resolution while employing only 8-bit capacitor-DAC array. The prototype ADC is designed in 40nm CMOS technology, with a peak signal-to-noise-distortion ratio (SNDR) 59 dB and 68 dB spurious-free-dynamic-range (SFDR) at 160 MS/s sampling frequency, while consuming 1 mW power from 1.1 V supply voltage. The figure-of-merit (FoM) is 34.29 fJ/conv.-step.","PeriodicalId":127121,"journal":{"name":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 2nd International Conference on Circuits, System and Simulation (ICCSS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CIRSYSSIM.2018.8525985","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 10-bit 160MS/s 20MHz bandwidth low-power noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) using a novel dynamic amplifier-based filter is presented. Thanks to noise-shaping architecture, the proposed scheme can achieve 10-bit resolution while employing only 8-bit capacitor-DAC array. The prototype ADC is designed in 40nm CMOS technology, with a peak signal-to-noise-distortion ratio (SNDR) 59 dB and 68 dB spurious-free-dynamic-range (SFDR) at 160 MS/s sampling frequency, while consuming 1 mW power from 1.1 V supply voltage. The figure-of-merit (FoM) is 34.29 fJ/conv.-step.