Octagon architecture for low power and high performance NoC design

Abstract

Network-on-Chip (NoC) architectures have been shown to solve on chip communication issues in larger SoC designs, but its success heavily depends on the total power budget they may require. Designing power efficient NoCs or finding ways to reduce NoC power is thus extremely important. In this paper, power efficiency of Synchronous and Asynchronous Octagon NoC architectures is presented. The relation between ccdata (the activity factor of the data transfers between the two switches) and power efficiency of the two networks is analyzed. Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfers between two switches (celata) satisfies a particular range. The area of Asynchronous switch is increased by 25% as compared to Synchronous switch. However the power dissipation of the Asynchronous architecture is decreased by 27% in comparison to the power dissipation of the Synchronous architecture when adata equals 0.2 and the activity factor of the control signals is 1/64 of the adata. The total metal resources required to implement Asynchronous design are decreased by 4 %.