A 40-Gb/s quarter rate CDR with 1∶4 demultiplexer in 90-nm CMOS technology

Abstract

This paper presents a 40-Gb/s phase-locked clock and data recovery (CDR) circuit with 1∶4 demultiplexer in IBM 90-nm CMOS technology. The CDR circuit incorporates an inductorless eight-phase LC voltage-controlled oscillator (VCO) and a quarter-rate bang-bang phase detector (PD). A novel inductorless eight-phase LC VCO including four LC oscillator cells is presented to generate the eight-phase outputs. A one-forth-rate phase detector employing eight flip-flops is proposed. The 40-Gb/s input data are sampled with eight parallel different-ial master-salve flip-flops every 12.5 ps and the 40-Gb/s data are demultiplexed into four 10-Gb/s outputs when the CDR circuit is locked. The recovered clock exhibits 200mV output swing and a jitter of 0.2 psrms and 0.6 pspp. The retimed data exhibits 200mV output swing and a jitter of 0.5 psrms and 2.1 pspp. The CDR circuit consumes 72 mW from a 1.2 V supply excluding out buffers.