A new generalized state-space dynamic neural network method for I/O buffer modeling in high-speed PCB design

Abstract

In this paper, we present a new method for modeling the nonlinear transient behavior of I/O buffers in high-speed PCB design. The proposed method expands the existing StateSpace Dynamic Neural Network (SSDNN) into a more generalized and efficient technique for modeling nonlinear behavior of I/O buffers. A Multi-Layer Perceptron (MLP) neural network with multiple hidden layers is combined with the SSDNN framework to further enhance the accuracy and flexibility of the trained neural network models. In addition, a new formulation embedding finite delay elements into the existing SSDNN is proposed to effectively address the modeling of such I/O devices where a long propagation delay is present. The proposed method is applied to the behavioral modeling of a commercial SSTL output buffer. It is demonstrated that the proposed method provides better accuracy compared to the existing SSDNN for modeling I/O buffers with strong nonlinearity and a long propagation delay, while outperforming the detailed SPICE model in terms of simulation efficiency.