Energy Efficient High Performance Adder/Subtractor Circuits

G. Ramesh, P. Manikandan, P. Naveen, M. Saravanan, S. R. Ashok Kumar, C. Swedheetha
{"title":"Energy Efficient High Performance Adder/Subtractor Circuits","authors":"G. Ramesh, P. Manikandan, P. Naveen, M. Saravanan, S. R. Ashok Kumar, C. Swedheetha","doi":"10.1109/ICOSEC54921.2022.9952136","DOIUrl":null,"url":null,"abstract":"Integrated circuit has been widely used in different applications. The design and development of CMOS transistor provides various advantages such as low power dissipation, cost efficient solutions, enhanced processor performance and size reduction. The main aim of the proposed research work is to increase the performance of the processor and reduce the area by increasing the performance of the adder circuits. The adder circuits enable its availability in many processors. In the processor, ALU is considered as the main functional block for performing any arithmetic operations. A novel high performance adders circuits were designed with the 0.18μm technology in TSMC Spice Simulator. Pass transistor logic has been used to reduce the transistors count in the circuit and hence the performance has increased by 10% when compared with the existing CMOS structure.","PeriodicalId":221953,"journal":{"name":"2022 3rd International Conference on Smart Electronics and Communication (ICOSEC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 3rd International Conference on Smart Electronics and Communication (ICOSEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICOSEC54921.2022.9952136","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Integrated circuit has been widely used in different applications. The design and development of CMOS transistor provides various advantages such as low power dissipation, cost efficient solutions, enhanced processor performance and size reduction. The main aim of the proposed research work is to increase the performance of the processor and reduce the area by increasing the performance of the adder circuits. The adder circuits enable its availability in many processors. In the processor, ALU is considered as the main functional block for performing any arithmetic operations. A novel high performance adders circuits were designed with the 0.18μm technology in TSMC Spice Simulator. Pass transistor logic has been used to reduce the transistors count in the circuit and hence the performance has increased by 10% when compared with the existing CMOS structure.
高效节能的高性能加/减电路
集成电路已广泛应用于不同的应用领域。CMOS晶体管的设计和开发提供了各种优势,如低功耗,低成本的解决方案,增强处理器性能和缩小尺寸。提出的研究工作的主要目的是通过提高加法器电路的性能来提高处理器的性能并减小其面积。加法器电路使其在许多处理器中可用。在处理器中,ALU被认为是执行任何算术运算的主要功能块。采用0.18μm技术,在台积电Spice模拟器上设计了一种新型的高性能加法电路。通过晶体管逻辑来减少电路中的晶体管数量,因此与现有的CMOS结构相比,性能提高了10%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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